the signals and their derived score are provisional and subject to change.
validate manually before sharing.
9adbba8622f378253765b7d438b6cbcc4d03fc579adbba8622f33 months agoCo-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com># CLAUDE.md
This file provides guidance to Claude Code (claude.ai/code) when working with code in this repository.
## Project Overview
This is an Apple IIgs hardware simulation written in Verilog using the Verilator simulator. The project implements a cycle-accurate emulation of the Apple IIgs computer system, including the 65C816 CPU, video graphics controller (VGC), sound system (ES5503), and various peripherals.
The goal is to run this code on an FPGA. Don't make any changes to memory or clocks that none