github.com/hxxdev/LazyVerilog

(link)
score
3 (F)
mode
Full
last commit
b9c9df145f6d51cebe1e5ad71958fdd9f2c58752
analyzed on
Sat, 13 Jun 2026 16:42:24 +0000
total evidence
31

commit signals (29)

source signals (2)